Veri cation of All Circuits in a Floating - Point UnitUsing Word - Level Model

This paper presents the formal veriication of all sub-circuits in a oating-point arithmetic unit (FPU) from an Intel microprocessor using a word-level model checker. This work represents the rst large-scale application of word-level model checking techniques. The FPU can perform addition, subtraction, multiplication, square root, division, remainder, and rounding operations; verifying such a broad range of function-ality required coupling the model checker with a number of other techniques, such as property decomposition, property speciic model abstraction, and latch removal. We will illustrate the veriication techniques used by us with respect to the design of the Weitek WTL3170/3171 Sparc oating point coprocessor. The principal contribution of this paper is a practical veriication methodology explaining what techniques to apply (and where to apply them) when verifying oating-point arithmetic circuits. We have applied our methods to the oating-point unit of a state-of-the-art Intel microprocessor, which is capable of extended precision (64-bit mantissa) computation. The success of this eeort demonstrates that word-level model checking, with the help of other veriication techniques, can verify arithmetic circuits of the size and complexity found in industry.